SoC Front-End Engineer (Junior–Principal) | RTL & Architecture

NSING, part of Nations Technologies Group, is hiring an RTL Design Engineer in Singapore. You will develop synthesizable RTL in Verilog/SystemVerilog, design I2C/XSPI blocks and DMA controllers, and contribute to architecture discussions and PPA trade-offs. You will build self-test environments, collaborate with verification and backend teams, and ensure design quality through linting and timing closure activities. A strong foundation in digital IC design is essential. J-18808-Ljbffr

Summary and match are AI-generated; verify details on the original posting.

Listed via Adzuna. All sources